Evaluation of microwave circuits for radar receivers with reduced complexity

Research focused on methods to reduce radar receiver complexity and size has been going on at FOI. The main goal has been to reduce the number of down-converting stages in frequency hopping radar receivers with a large bandwidth and thereby reduce the receiver complexity and size. A receiver based on only one down-converting stage set the demands on the image rejection filter to be narrow band, but also agile over the whole radar bandwidth. The filter must therefore be tunable. To get sufficiently high image rejection a tunable filter could be combined with an image rejection mixer. This report describes the background of the research focused on methods to reduce radar receiver complexity and size. Examples of manufactured circuits are presented. In the discussion chapter the possibilities for our ideas are treated and we proposed a one -chip radar receiver chip solution. The report is concluded with a list of publications by FOI in the field.